1. Field of the Invention
This invention relates to a semiconductor memory device, especially relates to a NAND-type EEPROM with electrically rewritable and non-volatile memory cells.
2. Description of Related Art
A NAND-type flash memory is known as one of electrically rewritable and non-volatile semiconductor memory devices (EEPROMs). A basic unit of the NAND-type flash memory, i.e., NAND cell unit, is formed of plural memory cells connected in series and two select transistors disposed at both ends thereof. One of the select transistors is coupled to a bit line, and the other to a source line disposed common to a memory cell array.
The NAND-type flash memory basically stores a binary data in a memory cell, as shown in FIG. 18, logic “1” and “0” of which are defined by a low threshold state (usually, negative threshold state) and a high threshold state (usually, positive threshold state), respectively. To store data with a large capacity, a multi-value storing (for example, four-value storing) scheme may be utilized. To prevent the memory from being erroneously read, it is required to set separation voltage areas between the respective data threshold distributions.
In case of binary data storing, write voltage application and verify-read operation for verifying the written state will be repeated for securing the lower limit, Vthw, of “0” data threshold voltage. Usually, data write is done by a page defined as a set of memory cells arranged along a word line.
Data erase is done by a block defined as a set of NAND cell units arranged along a word line. In this case also, erase voltage application and verify-read operation for verifying the erased state will be repeated for securing the upper limit, Vthe, of “1” data threshold voltage.
In the above-described data write and erase schemes, the lower limit Vthw of “0” data threshold voltage and the upper limit Vthe of “1” data threshold voltage may be guaranteed. However, it can not be recognized what are these threshold distributions like in detail. To estimate properties of a memory chip, it becomes important to know what threshold distributions have been obtained in detail. For measuring data threshold voltage distributions, it is required to repeat read current detection with scanning a read voltage applied to a selected memory cell. It has already been provided a memory scheme with a test mode, in which an external read voltage is applied to measure the threshold voltage distributions (for example, refer to Published and Unexamined Japanese Patent Application No. 3-283200).
As described above, select transistors are disposed at both ends of each NAND cell unit, and these properties have not a little influence on the read and/or write properties. Usually, estimation of threshold voltages of the select transistors is depending on only measuring test devices (TEG) formed along scribe lines of a memory wafer.
However, since the select transistors in the memory cell array are formed simultaneously with the memory cells to have a specific shape as different from that of memory cells, it is difficult to accurately estimate the select transistor's properties based on measuring the properties of the TEG devices. Especially, as the memory cells are miniaturized more, it becomes more important to accurately estimate the properties of select transistors.